This is for only the GBA's ARMv4TM Opcode Syntax Desciption Condition field 0000 eq i If Zero set cmp: if equal 0001 ne i If Zero clear cmp: if not equal 0010 cs i If Carry set cmp: if unsigned higher or same 0011 cc i If Carry clear cmp: if unsigned lower 0100 mi i If Negative set cmp: if negative 0101 pl i If Negative clear cmp: if positive 0110 vs i If oVerflow set cmp: if became positive 0111 vc i If oVerflow clear cmp: if not became positive 1000 hi i If Carry set + Zero clear cmp: if unsigned higher 1001 ls i If Carry clear / Zero clear cmp: if unsigned lower or same 1010 ge i If Negative=oVerflow cmp: if signed greater or equal 1011 lt i If Negative!=oVerflow cmp: if signed less than 1100 gt i If Zero clear + Negative=oVerflow cmp: if signed greater than 1101 le i If Zero set / Negative!=oVerflow cmp: if signed less than or equal Branch register instruction cccc 00010010111111111111 0001 ssss bx rs Branch to rs Branch instructions cccc 101 0 iiiiiiiiiiiiiiiiiiiiiiii b pc,#i Branch ąi<<2 instructions after next cccc 101 1 iiiiiiiiiiiiiiiiiiiiiiii bl pc,#i Save pc|1 to lr and branch ąi<<2 instructions Logical/arithmetic instructions cccc 00 0 0000 0 ssss dddd iiiii 00 0 vvvv and rd,rs,rv,lsl #i AND, preserving CPSR, rs, to rd, by rv<>i cccc 00 0 0000 0 ssss dddd 00000 01 0 vvvv and rd,rs,rv,lsr #0x20 AND, preserving CPSR, rs, to rd, by rv>>32 cccc 00 0 0000 0 ssss dddd iiiii 10 0 vvvv and rd,rs,rv,asr #i AND, preserving CPSR, rs, to rd, by rvą>>i cccc 00 0 0000 0 ssss dddd 00000 10 0 vvvv and rd,rs,rv,asr #0x20 AND, preserving CPSR, rs, to rd, by rvą>>32 cccc 00 0 0000 0 ssss dddd iiiii 11 0 vvvv and rd,rs,rv,ror #i AND, preserving CPSR, rs, to rd, by rv ror i cccc 00 0 0000 0 ssss dddd 00000 11 0 vvvv and rd,rs,rv,rrx #1 AND, preserving CPSR, rs, to rd, by rv rrx 1 cccc 00 0 0000 0 ssss dddd rrrr0 00 1 vvvv and rd,rs,rv,lsl rr AND, preserving CPSR, rs, to rd, by rv<>rr cccc 00 0 0000 0 ssss dddd rrrr0 11 1 vvvv and rd,rs,rv,ror rr AND, preserving CPSR, rs, to rd, by rv ror rr cccc 00 0 0000 1 ssss dddd iiiii 00 0 vvvv ands rd,rs,rv,lsl #i AND rs, to rd, by rv<>i cccc 00 0 0000 1 ssss dddd 00000 01 0 vvvv ands rd,rs,rv,lsr #0x20 AND rs, to rd, by rv>>32 cccc 00 0 0000 1 ssss dddd iiiii 10 0 vvvv ands rd,rs,rv,asr #i AND rs, to rd, by rvą>>i cccc 00 0 0000 1 ssss dddd 00000 10 0 vvvv ands rd,rs,rv,asr #0x20 AND rs, to rd, by rvą>>32 cccc 00 0 0000 1 ssss dddd iiiii 11 0 vvvv ands rd,rs,rv,ror #i AND rs, to rd, by rv ror i cccc 00 0 0000 1 ssss dddd 00000 11 0 vvvv ands rd,rs,rv,rrx #1 AND rs, to rd, by rv rrx 1 cccc 00 0 0000 1 ssss dddd rrrr0 00 1 vvvv ands rd,rs,rv,lsl rr AND rs, to rd, by rv<>rr cccc 00 0 0000 1 ssss dddd rrrr0 10 1 vvvv ands rd,rs,rv,asr rr AND rs, to rd, by rvą>>rr cccc 00 0 0000 1 ssss dddd rrrr0 11 1 vvvv ands rd,rs,rv,ror rr AND rs, to rd, by rv ror rr cccc 00 1 0000 0 ssss dddd iiii vvvvvvvv and rd,rs,#iv AND, preserving CPSR, rs, to rd, by v ror i<<1 cccc 00 1 0000 1 ssss dddd iiii vvvvvvvv ands rd,rs,#iv AND rs, to rd, by v ror i<<1 cccc 00 0 0001 0 ssss dddd iiiii 00 0 vvvv eor rd,rs,rv,lsl #i XOR, preserving CPSR, rs, to rd, and rv<>i cccc 00 0 0001 0 ssss dddd 00000 01 0 vvvv eor rd,rs,rv,lsr #0x20 XOR, preserving CPSR, rs, to rd, and rv>>32 cccc 00 0 0001 0 ssss dddd iiiii 10 0 vvvv eor rd,rs,rv,asr #i XOR, preserving CPSR, rs, to rd, and rvą>>i cccc 00 0 0001 0 ssss dddd 00000 10 0 vvvv eor rd,rs,rv,asr #0x20 XOR, preserving CPSR, rs, to rd, and rvą>>32 cccc 00 0 0001 0 ssss dddd iiiii 11 0 vvvv eor rd,rs,rv,ror #i XOR, preserving CPSR, rs, to rd, and rv ror i cccc 00 0 0001 0 ssss dddd 00000 11 0 vvvv eor rd,rs,rv,rrx #1 XOR, preserving CPSR, rs, to rd, and rv rrx 1 cccc 00 0 0001 0 ssss dddd rrrr0 00 1 vvvv eor rd,rs,rv,lsl rr XOR, preserving CPSR, rs, to rd, and rv<>rr cccc 00 0 0001 0 ssss dddd rrrr0 11 1 vvvv eor rd,rs,rv,ror rr XOR, preserving CPSR, rs, to rd, and rv ror rr cccc 00 0 0001 1 ssss dddd iiiii 00 0 vvvv eors rd,rs,rv,lsl #i XOR rs, to rd, and rv<>i cccc 00 0 0001 1 ssss dddd 00000 01 0 vvvv eors rd,rs,rv,lsr #0x20 XOR rs, to rd, and rv>>32 cccc 00 0 0001 1 ssss dddd iiiii 10 0 vvvv eors rd,rs,rv,asr #i XOR rs, to rd, and rvą>>i cccc 00 0 0001 1 ssss dddd 00000 10 0 vvvv eors rd,rs,rv,asr #0x20 XOR rs, to rd, and rvą>>32 cccc 00 0 0001 1 ssss dddd iiiii 11 0 vvvv eors rd,rs,rv,ror #i XOR rs, to rd, and rv ror i cccc 00 0 0001 1 ssss dddd 00000 11 0 vvvv eors rd,rs,rv,rrx #1 XOR rs, to rd, and rv rrx 1 cccc 00 0 0001 1 ssss dddd rrrr0 00 1 vvvv eors rd,rs,rv,lsl rr XOR rs, to rd, and rv<>rr cccc 00 0 0001 1 ssss dddd rrrr0 10 1 vvvv eors rd,rs,rv,asr rr XOR rs, to rd, and rvą>>rr cccc 00 0 0001 1 ssss dddd rrrr0 11 1 vvvv eors rd,rs,rv,ror rr XOR rs, to rd, and rv ror rr cccc 00 1 0001 0 ssss dddd iiii vvvvvvvv eor rd,rs,#iv XOR, preserving CPSR, rs, to rd, and v ror i<<1 cccc 00 1 0001 1 ssss dddd iiii vvvvvvvv eors rd,rs,#iv XOR rs, to rd, and v ror i<<1 cccc 00 0 0010 0 ssss dddd iiiii 00 0 vvvv sub rd,rs,rv,lsl #i Subtract, preserving CPSR, rs, to rd, by rv<>i cccc 00 0 0010 0 ssss dddd 00000 01 0 vvvv sub rd,rs,rv,lsr #0x20 Subtract, preserving CPSR, rs, to rd, by rv>>32 cccc 00 0 0010 0 ssss dddd iiiii 10 0 vvvv sub rd,rs,rv,asr #i Subtract, preserving CPSR, rs, to rd, by rvą>>i cccc 00 0 0010 0 ssss dddd 00000 10 0 vvvv sub rd,rs,rv,asr #0x20 Subtract, preserving CPSR, rs, to rd, by rvą>>32 cccc 00 0 0010 0 ssss dddd iiiii 11 0 vvvv sub rd,rs,rv,ror #i Subtract, preserving CPSR, rs, to rd, by rv ror i cccc 00 0 0010 0 ssss dddd 00000 11 0 vvvv sub rd,rs,rv,rrx #1 Subtract, preserving CPSR, rs, to rd, by rv rrx 1 cccc 00 0 0010 0 ssss dddd rrrr0 00 1 vvvv sub rd,rs,rv,lsl rr Subtract, preserving CPSR, rs, to rd, by rv<>rr cccc 00 0 0010 0 ssss dddd rrrr0 11 1 vvvv sub rd,rs,rv,ror rr Subtract, preserving CPSR, rs, to rd, by rv ror rr cccc 00 0 0010 1 ssss dddd iiiii 00 0 vvvv subs rd,rs,rv,lsl #i Subtract rs, to rd, by rv<>i cccc 00 0 0010 1 ssss dddd 00000 01 0 vvvv subs rd,rs,rv,lsr #0x20 Subtract rs, to rd, by rv>>32 cccc 00 0 0010 1 ssss dddd iiiii 10 0 vvvv subs rd,rs,rv,asr #i Subtract rs, to rd, by rvą>>i cccc 00 0 0010 1 ssss dddd 00000 10 0 vvvv subs rd,rs,rv,asr #0x20 Subtract rs, to rd, by rvą>>32 cccc 00 0 0010 1 ssss dddd iiiii 11 0 vvvv subs rd,rs,rv,ror #i Subtract rs, to rd, by rv ror i cccc 00 0 0010 1 ssss dddd 00000 11 0 vvvv subs rd,rs,rv,rrx #1 Subtract rs, to rd, by rv rrx 1 cccc 00 0 0010 1 ssss dddd rrrr0 00 1 vvvv subs rd,rs,rv,lsl rr Subtract rs, to rd, by rv<>rr cccc 00 0 0010 1 ssss dddd rrrr0 10 1 vvvv subs rd,rs,rv,asr rr Subtract rs, to rd, by rvą>>rr cccc 00 0 0010 1 ssss dddd rrrr0 11 1 vvvv subs rd,rs,rv,ror rr Subtract rs, to rd, by rv ror rr cccc 00 1 0010 0 ssss dddd iiii vvvvvvvv sub rd,rs,#iv Subtract, preserving CPSR, rs, to rd, by v ror i<<1 cccc 00 1 0010 1 ssss dddd iiii vvvvvvvv subs rd,rs,#iv Subtract rs, to rd, by v ror i<<1 cccc 00 0 0011 0 ssss dddd iiiii 00 0 vvvv rsb rd,rs,rv,lsl #i Subtract, preserving CPSR, rs, to rd, from rv<>i cccc 00 0 0011 0 ssss dddd 00000 01 0 vvvv rsb rd,rs,rv,lsr #0x20 Subtract, preserving CPSR, rs, to rd, from rv>>32 cccc 00 0 0011 0 ssss dddd iiiii 10 0 vvvv rsb rd,rs,rv,asr #i Subtract, preserving CPSR, rs, to rd, from rvą>>i cccc 00 0 0011 0 ssss dddd 00000 10 0 vvvv rsb rd,rs,rv,asr #0x20 Subtract, preserving CPSR, rs, to rd, from rvą>>32 cccc 00 0 0011 0 ssss dddd iiiii 11 0 vvvv rsb rd,rs,rv,ror #i Subtract, preserving CPSR, rs, to rd, from rv ror i cccc 00 0 0011 0 ssss dddd 00000 11 0 vvvv rsb rd,rs,rv,rrx #1 Subtract, preserving CPSR, rs, to rd, from rv rrx 1 cccc 00 0 0011 0 ssss dddd rrrr0 00 1 vvvv rsb rd,rs,rv,lsl rr Subtract, preserving CPSR, rs, to rd, from rv<>rr cccc 00 0 0011 0 ssss dddd rrrr0 11 1 vvvv rsb rd,rs,rv,ror rr Subtract, preserving CPSR, rs, to rd, from rv ror rr cccc 00 0 0011 1 ssss dddd iiiii 00 0 vvvv rsbs rd,rs,rv,lsl #i Subtract rs, to rd, from rv<>i cccc 00 0 0011 1 ssss dddd 00000 01 0 vvvv rsbs rd,rs,rv,lsr #0x20 Subtract rs, to rd, from rv>>32 cccc 00 0 0011 1 ssss dddd iiiii 10 0 vvvv rsbs rd,rs,rv,asr #i Subtract rs, to rd, from rvą>>i cccc 00 0 0011 1 ssss dddd 00000 10 0 vvvv rsbs rd,rs,rv,asr #0x20 Subtract rs, to rd, from rvą>>32 cccc 00 0 0011 1 ssss dddd iiiii 11 0 vvvv rsbs rd,rs,rv,ror #i Subtract rs, to rd, from rv ror i cccc 00 0 0011 1 ssss dddd 00000 11 0 vvvv rsbs rd,rs,rv,rrx #1 Subtract rs, to rd, from rv rrx 1 cccc 00 0 0011 1 ssss dddd rrrr0 00 1 vvvv rsbs rd,rs,rv,lsl rr Subtract rs, to rd, from rv<>rr cccc 00 0 0011 1 ssss dddd rrrr0 10 1 vvvv rsbs rd,rs,rv,asr rr Subtract rs, to rd, from rvą>>rr cccc 00 0 0011 1 ssss dddd rrrr0 11 1 vvvv rsbs rd,rs,rv,ror rr Subtract rs, to rd, from rv ror rr cccc 00 1 0011 0 ssss dddd iiii vvvvvvvv rsb rd,rs,#iv Subtract, preserving CPSR, rs, to rd, from v ror i<<1 cccc 00 1 0011 1 ssss dddd iiii vvvvvvvv rsbs rd,rs,#iv Subtract rs, to rd, from v ror i<<1 cccc 00 0 0100 0 ssss dddd iiiii 00 0 vvvv add rd,rs,rv,lsl #i Add, preserving CPSR, rs, to rd, and rv<>i cccc 00 0 0100 0 ssss dddd 00000 01 0 vvvv add rd,rs,rv,lsr #0x20 Add, preserving CPSR, rs, to rd, and rv>>32 cccc 00 0 0100 0 ssss dddd iiiii 10 0 vvvv add rd,rs,rv,asr #i Add, preserving CPSR, rs, to rd, and rvą>>i cccc 00 0 0100 0 ssss dddd 00000 10 0 vvvv add rd,rs,rv,asr #0x20 Add, preserving CPSR, rs, to rd, and rvą>>32 cccc 00 0 0100 0 ssss dddd iiiii 11 0 vvvv add rd,rs,rv,ror #i Add, preserving CPSR, rs, to rd, and rv ror i cccc 00 0 0100 0 ssss dddd 00000 11 0 vvvv add rd,rs,rv,rrx #1 Add, preserving CPSR, rs, to rd, and rv rrx 1 cccc 00 0 0100 0 ssss dddd rrrr0 00 1 vvvv add rd,rs,rv,lsl rr Add, preserving CPSR, rs, to rd, and rv<>rr cccc 00 0 0100 0 ssss dddd rrrr0 11 1 vvvv add rd,rs,rv,ror rr Add, preserving CPSR, rs, to rd, and rv ror rr cccc 00 0 0100 1 ssss dddd iiiii 00 0 vvvv adds rd,rs,rv,lsl #i Add rs, to rd, and rv<>i cccc 00 0 0100 1 ssss dddd 00000 01 0 vvvv adds rd,rs,rv,lsr #0x20 Add rs, to rd, and rv>>32 cccc 00 0 0100 1 ssss dddd iiiii 10 0 vvvv adds rd,rs,rv,asr #i Add rs, to rd, and rvą>>i cccc 00 0 0100 1 ssss dddd 00000 10 0 vvvv adds rd,rs,rv,asr #0x20 Add rs, to rd, and rvą>>32 cccc 00 0 0100 1 ssss dddd iiiii 11 0 vvvv adds rd,rs,rv,ror #i Add rs, to rd, and rv ror i cccc 00 0 0100 1 ssss dddd 00000 11 0 vvvv adds rd,rs,rv,rrx #1 Add rs, to rd, and rv rrx 1 cccc 00 0 0100 1 ssss dddd rrrr0 00 1 vvvv adds rd,rs,rv,lsl rr Add rs, to rd, and rv<>rr cccc 00 0 0100 1 ssss dddd rrrr0 10 1 vvvv adds rd,rs,rv,asr rr Add rs, to rd, and rvą>>rr cccc 00 0 0100 1 ssss dddd rrrr0 11 1 vvvv adds rd,rs,rv,ror rr Add rs, to rd, and rv ror rr cccc 00 1 0100 0 ssss dddd iiii vvvvvvvv add rd,rs,#iv Add, preserving CPSR, rs, to rd, and v ror i<<1 cccc 00 1 0100 1 ssss dddd iiii vvvvvvvv adds rd,rs,#iv Add rs, to rd, and v ror i<<1 cccc 00 0 0101 0 ssss dddd iiiii 00 0 vvvv adc rd,rs,rv,lsl #i Add, preserving CPSR, rs, to rd, and rv<>i with carry cccc 00 0 0101 0 ssss dddd 00000 01 0 vvvv adc rd,rs,rv,lsr #0x20 Add, preserving CPSR, rs, to rd, and rv>>32 with carry cccc 00 0 0101 0 ssss dddd iiiii 10 0 vvvv adc rd,rs,rv,asr #i Add, preserving CPSR, rs, to rd, and rvą>>i with carry cccc 00 0 0101 0 ssss dddd 00000 10 0 vvvv adc rd,rs,rv,asr #0x20 Add, preserving CPSR, rs, to rd, and rvą>>32 with carry cccc 00 0 0101 0 ssss dddd iiiii 11 0 vvvv adc rd,rs,rv,ror #i Add, preserving CPSR, rs, to rd, and rv ror i with carry cccc 00 0 0101 0 ssss dddd 00000 11 0 vvvv adc rd,rs,rv,rrx #1 Add, preserving CPSR, rs, to rd, and rv rrx 1 with carry cccc 00 0 0101 0 ssss dddd rrrr0 00 1 vvvv adc rd,rs,rv,lsl rr Add, preserving CPSR, rs, to rd, and rv<>rr with carry cccc 00 0 0101 0 ssss dddd rrrr0 11 1 vvvv adc rd,rs,rv,ror rr Add, preserving CPSR, rs, to rd, and rv ror rr with carry cccc 00 0 0101 1 ssss dddd iiiii 00 0 vvvv adcs rd,rs,rv,lsl #i Add rs, to rd, and rv<>i with carry cccc 00 0 0101 1 ssss dddd 00000 01 0 vvvv adcs rd,rs,rv,lsr #0x20 Add rs, to rd, and rv>>32 with carry cccc 00 0 0101 1 ssss dddd iiiii 10 0 vvvv adcs rd,rs,rv,asr #i Add rs, to rd, and rvą>>i with carry cccc 00 0 0101 1 ssss dddd 00000 10 0 vvvv adcs rd,rs,rv,asr #0x20 Add rs, to rd, and rvą>>32 with carry cccc 00 0 0101 1 ssss dddd iiiii 11 0 vvvv adcs rd,rs,rv,ror #i Add rs, to rd, and rv ror i with carry cccc 00 0 0101 1 ssss dddd 00000 11 0 vvvv adcs rd,rs,rv,rrx #1 Add rs, to rd, and rv rrx 1 with carry cccc 00 0 0101 1 ssss dddd rrrr0 00 1 vvvv adcs rd,rs,rv,lsl rr Add rs, to rd, and rv<>rr with carry cccc 00 0 0101 1 ssss dddd rrrr0 10 1 vvvv adcs rd,rs,rv,asr rr Add rs, to rd, and rvą>>rr with carry cccc 00 0 0101 1 ssss dddd rrrr0 11 1 vvvv adcs rd,rs,rv,ror rr Add rs, to rd, and rv ror rr with carry cccc 00 1 0101 0 ssss dddd iiii vvvvvvvv adc rd,rs,#iv Add, preserving CPSR, rs, to rd, and v ror i<<1 with carry cccc 00 1 0101 1 ssss dddd iiii vvvvvvvv adcs rd,rs,#iv Add rs, to rd, and v ror i<<1 with carry cccc 00 0 0110 0 ssss dddd iiiii 00 0 vvvv sbc rd,rs,rv,lsl #i Subtract, preserving CPSR, rs, to rd, by rv<>i with carry cccc 00 0 0110 0 ssss dddd 00000 01 0 vvvv sbc rd,rs,rv,lsr #0x20 Subtract, preserving CPSR, rs, to rd, by rv>>32 with carry cccc 00 0 0110 0 ssss dddd iiiii 10 0 vvvv sbc rd,rs,rv,asr #i Subtract, preserving CPSR, rs, to rd, by rvą>>i with carry cccc 00 0 0110 0 ssss dddd 00000 10 0 vvvv sbc rd,rs,rv,asr #0x20 Subtract, preserving CPSR, rs, to rd, by rvą>>32 with carry cccc 00 0 0110 0 ssss dddd iiiii 11 0 vvvv sbc rd,rs,rv,ror #i Subtract, preserving CPSR, rs, to rd, by rv ror i with carry cccc 00 0 0110 0 ssss dddd 00000 11 0 vvvv sbc rd,rs,rv,rrx #1 Subtract, preserving CPSR, rs, to rd, by rv rrx 1 with carry cccc 00 0 0110 0 ssss dddd rrrr0 00 1 vvvv sbc rd,rs,rv,lsl rr Subtract, preserving CPSR, rs, to rd, by rv<>rr with carry cccc 00 0 0110 0 ssss dddd rrrr0 11 1 vvvv sbc rd,rs,rv,ror rr Subtract, preserving CPSR, rs, to rd, by rv ror rr with carry cccc 00 0 0110 1 ssss dddd iiiii 00 0 vvvv sbcs rd,rs,rv,lsl #i Subtract rs, to rd, by rv<>i with carry cccc 00 0 0110 1 ssss dddd 00000 01 0 vvvv sbcs rd,rs,rv,lsr #0x20 Subtract rs, to rd, by rv>>32 with carry cccc 00 0 0110 1 ssss dddd iiiii 10 0 vvvv sbcs rd,rs,rv,asr #i Subtract rs, to rd, by rvą>>i with carry cccc 00 0 0110 1 ssss dddd 00000 10 0 vvvv sbcs rd,rs,rv,asr #0x20 Subtract rs, to rd, by rvą>>32 with carry cccc 00 0 0110 1 ssss dddd iiiii 11 0 vvvv sbcs rd,rs,rv,ror #i Subtract rs, to rd, by rv ror i with carry cccc 00 0 0110 1 ssss dddd 00000 11 0 vvvv sbcs rd,rs,rv,rrx #1 Subtract rs, to rd, by rv rrx 1 with carry cccc 00 0 0110 1 ssss dddd rrrr0 00 1 vvvv sbcs rd,rs,rv,lsl rr Subtract rs, to rd, by rv<>rr with carry cccc 00 0 0110 1 ssss dddd rrrr0 10 1 vvvv sbcs rd,rs,rv,asr rr Subtract rs, to rd, by rvą>>rr with carry cccc 00 0 0110 1 ssss dddd rrrr0 11 1 vvvv sbcs rd,rs,rv,ror rr Subtract rs, to rd, by rv ror rr with carry cccc 00 1 0110 0 ssss dddd iiii vvvvvvvv sbc rd,rs,#iv Subtract, preserving CPSR, rs, to rd, by v ror i<<1 with carry cccc 00 1 0110 1 ssss dddd iiii vvvvvvvv sbcs rd,rs,#iv Subtract rs, to rd, by v ror i<<1 with carry cccc 00 0 0111 0 ssss dddd iiiii 00 0 vvvv rsc rd,rs,rv,lsl #i Subtract, preserving CPSR, rs, to rd, from rv<>i cccc 00 0 0111 0 ssss dddd 00000 01 0 vvvv rsc rd,rs,rv,lsr #0x20 Subtract, preserving CPSR, rs, to rd, from rv>>32 cccc 00 0 0111 0 ssss dddd iiiii 10 0 vvvv rsc rd,rs,rv,asr #i Subtract, preserving CPSR, rs, to rd, from rvą>>i cccc 00 0 0111 0 ssss dddd 00000 10 0 vvvv rsc rd,rs,rv,asr #0x20 Subtract, preserving CPSR, rs, to rd, from rvą>>32 cccc 00 0 0111 0 ssss dddd iiiii 11 0 vvvv rsc rd,rs,rv,ror #i Subtract, preserving CPSR, rs, to rd, from rv ror i cccc 00 0 0111 0 ssss dddd 00000 11 0 vvvv rsc rd,rs,rv,rrx #1 Subtract, preserving CPSR, rs, to rd, from rv rrx 1 cccc 00 0 0111 0 ssss dddd rrrr0 00 1 vvvv rsc rd,rs,rv,lsl rr Subtract, preserving CPSR, rs, to rd, from rv<>rr cccc 00 0 0111 0 ssss dddd rrrr0 11 1 vvvv rsc rd,rs,rv,ror rr Subtract, preserving CPSR, rs, to rd, from rv ror rr cccc 00 0 0111 1 ssss dddd iiiii 00 0 vvvv rscs rd,rs,rv,lsl #i Subtract rs, to rd, from rv<>i cccc 00 0 0111 1 ssss dddd 00000 01 0 vvvv rscs rd,rs,rv,lsr #0x20 Subtract rs, to rd, from rv>>32 cccc 00 0 0111 1 ssss dddd iiiii 10 0 vvvv rscs rd,rs,rv,asr #i Subtract rs, to rd, from rvą>>i cccc 00 0 0111 1 ssss dddd 00000 10 0 vvvv rscs rd,rs,rv,asr #0x20 Subtract rs, to rd, from rvą>>32 cccc 00 0 0111 1 ssss dddd iiiii 11 0 vvvv rscs rd,rs,rv,ror #i Subtract rs, to rd, from rv ror i cccc 00 0 0111 1 ssss dddd 00000 11 0 vvvv rscs rd,rs,rv,rrx #1 Subtract rs, to rd, from rv rrx 1 cccc 00 0 0111 1 ssss dddd rrrr0 00 1 vvvv rscs rd,rs,rv,lsl rr Subtract rs, to rd, from rv<>rr cccc 00 0 0111 1 ssss dddd rrrr0 10 1 vvvv rscs rd,rs,rv,asr rr Subtract rs, to rd, from rvą>>rr cccc 00 0 0111 1 ssss dddd rrrr0 11 1 vvvv rscs rd,rs,rv,ror rr Subtract rs, to rd, from rv ror rr cccc 00 1 0111 0 ssss dddd iiii vvvvvvvv rsc rd,rs,#iv Subtract, preserving CPSR, rs, to rd, from v ror i<<1 cccc 00 1 0111 1 ssss dddd iiii vvvvvvvv rscs rd,rs,#iv Subtract rs, to rd, from v ror i<<1 cccc 00 0 1000 1 ssss 0000 iiiii 00 0 vvvv tst rs,rv,lsl #i Test rs by rv<>i cccc 00 0 1000 1 ssss 0000 00000 01 0 vvvv tst rs,rv,lsr #0x20 Test rs by rv>>32 cccc 00 0 1000 1 ssss 0000 iiiii 10 0 vvvv tst rs,rv,asr #i Test rs by rvą>>i cccc 00 0 1000 1 ssss 0000 00000 10 0 vvvv tst rs,rv,asr #0x20 Test rs by rvą>>32 cccc 00 0 1000 1 ssss 0000 iiiii 11 0 vvvv tst rs,rv,ror #i Test rs by rv ror i cccc 00 0 1000 1 ssss 0000 00000 11 0 vvvv tst rs,rv,rrx #1 Test rs by rv rrx 1 cccc 00 0 1000 1 ssss 0000 rrrr0 00 1 vvvv tst rs,rv,lsl rr Test rs by rv<>rr cccc 00 0 1000 1 ssss 0000 rrrr0 11 1 vvvv tst rs,rv,ror rr Test rs by rv ror rr cccc 00 1 1000 1 ssss 0000 iiii vvvvvvvv tst rs,#iv Test rs by v ror i<<1 cccc 00 0 1001 1 ssss 0000 iiiii 00 0 vvvv teq rs,rv,lsl #i XTest rs and rv<>i cccc 00 0 1001 1 ssss 0000 00000 01 0 vvvv teq rs,rv,lsr #0x20 XTest rs and rv>>32 cccc 00 0 1001 1 ssss 0000 iiiii 10 0 vvvv teq rs,rv,asr #i XTest rs and rvą>>i cccc 00 0 1001 1 ssss 0000 00000 10 0 vvvv teq rs,rv,asr #0x20 XTest rs and rvą>>32 cccc 00 0 1001 1 ssss 0000 iiiii 11 0 vvvv teq rs,rv,ror #i XTest rs and rv ror i cccc 00 0 1001 1 ssss 0000 00000 11 0 vvvv teq rs,rv,rrx #1 XTest rs and rv rrx 1 cccc 00 0 1001 1 ssss 0000 rrrr0 00 1 vvvv teq rs,rv,lsl rr XTest rs and rv<>rr cccc 00 0 1001 1 ssss 0000 rrrr0 11 1 vvvv teq rs,rv,ror rr XTest rs and rv ror rr cccc 00 1 1001 1 ssss 0000 iiii vvvvvvvv teq rs,#iv XTest rs and v ror i<<1 cccc 00 0 1010 1 ssss 0000 iiiii 00 0 vvvv cmp rs,rv,lsl #i Compare rs by rv<>i cccc 00 0 1010 1 ssss 0000 00000 01 0 vvvv cmp rs,rv,lsr #0x20 Compare rs by rv>>32 cccc 00 0 1010 1 ssss 0000 iiiii 10 0 vvvv cmp rs,rv,asr #i Compare rs by rvą>>i cccc 00 0 1010 1 ssss 0000 00000 10 0 vvvv cmp rs,rv,asr #0x20 Compare rs by rvą>>32 cccc 00 0 1010 1 ssss 0000 iiiii 11 0 vvvv cmp rs,rv,ror #i Compare rs by rv ror i cccc 00 0 1010 1 ssss 0000 00000 11 0 vvvv cmp rs,rv,rrx #1 Compare rs by rv rrx 1 cccc 00 0 1010 1 ssss 0000 rrrr0 00 1 vvvv cmp rs,rv,lsl rr Compare rs by rv<>rr cccc 00 0 1010 1 ssss 0000 rrrr0 11 1 vvvv cmp rs,rv,ror rr Compare rs by rv ror rr cccc 00 1 1010 1 ssss 0000 iiii vvvvvvvv cmp rs,#iv Compare rs by v ror i<<1 cccc 00 0 1011 1 ssss 0000 iiiii 00 0 vvvv cmn rs,rv,lsl #i Negative compare rs and rv<>i cccc 00 0 1011 1 ssss 0000 00000 01 0 vvvv cmn rs,rv,lsr #0x20 Negative compare rs and rv>>32 cccc 00 0 1011 1 ssss 0000 iiiii 10 0 vvvv cmn rs,rv,asr #i Negative compare rs and rvą>>i cccc 00 0 1011 1 ssss 0000 00000 10 0 vvvv cmn rs,rv,asr #0x20 Negative compare rs and rvą>>32 cccc 00 0 1011 1 ssss 0000 iiiii 11 0 vvvv cmn rs,rv,ror #i Negative compare rs and rv ror i cccc 00 0 1011 1 ssss 0000 00000 11 0 vvvv cmn rs,rv,rrx #1 Negative compare rs and rv rrx 1 cccc 00 0 1011 1 ssss 0000 rrrr0 00 1 vvvv cmn rs,rv,lsl rr Negative compare rs and rv<>rr cccc 00 0 1011 1 ssss 0000 rrrr0 11 1 vvvv cmn rs,rv,ror rr Negative compare rs and rv ror rr cccc 00 1 1011 1 ssss 0000 iiii vvvvvvvv cmn rs,#iv Negative compare rs and v ror i<<1 cccc 00 0 1100 0 ssss dddd iiiii 00 0 vvvv orr rd,rs,rv,lsl #i OR, preserving CPSR, rs, to rd, with rv<>i cccc 00 0 1100 0 ssss dddd 00000 01 0 vvvv orr rd,rs,rv,lsr #0x20 OR, preserving CPSR, rs, to rd, with rv>>32 cccc 00 0 1100 0 ssss dddd iiiii 10 0 vvvv orr rd,rs,rv,asr #i OR, preserving CPSR, rs, to rd, with rvą>>i cccc 00 0 1100 0 ssss dddd 00000 10 0 vvvv orr rd,rs,rv,asr #0x20 OR, preserving CPSR, rs, to rd, with rvą>>32 cccc 00 0 1100 0 ssss dddd iiiii 11 0 vvvv orr rd,rs,rv,ror #i OR, preserving CPSR, rs, to rd, with rv ror i cccc 00 0 1100 0 ssss dddd 00000 11 0 vvvv orr rd,rs,rv,rrx #1 OR, preserving CPSR, rs, to rd, with rv rrx 1 cccc 00 0 1100 0 ssss dddd rrrr0 00 1 vvvv orr rd,rs,rv,lsl rr OR, preserving CPSR, rs, to rd, with rv<>rr cccc 00 0 1100 0 ssss dddd rrrr0 11 1 vvvv orr rd,rs,rv,ror rr OR, preserving CPSR, rs, to rd, with rv ror rr cccc 00 0 1100 1 ssss dddd iiiii 00 0 vvvv orrs rd,rs,rv,lsl #i OR rs, to rd, with rv<>i cccc 00 0 1100 1 ssss dddd 00000 01 0 vvvv orrs rd,rs,rv,lsr #0x20 OR rs, to rd, with rv>>32 cccc 00 0 1100 1 ssss dddd iiiii 10 0 vvvv orrs rd,rs,rv,asr #i OR rs, to rd, with rvą>>i cccc 00 0 1100 1 ssss dddd 00000 10 0 vvvv orrs rd,rs,rv,asr #0x20 OR rs, to rd, with rvą>>32 cccc 00 0 1100 1 ssss dddd iiiii 11 0 vvvv orrs rd,rs,rv,ror #i OR rs, to rd, with rv ror i cccc 00 0 1100 1 ssss dddd 00000 11 0 vvvv orrs rd,rs,rv,rrx #1 OR rs, to rd, with rv rrx 1 cccc 00 0 1100 1 ssss dddd rrrr0 00 1 vvvv orrs rd,rs,rv,lsl rr OR rs, to rd, with rv<>rr cccc 00 0 1100 1 ssss dddd rrrr0 10 1 vvvv orrs rd,rs,rv,asr rr OR rs, to rd, with rvą>>rr cccc 00 0 1100 1 ssss dddd rrrr0 11 1 vvvv orrs rd,rs,rv,ror rr OR rs, to rd, with rv ror rr cccc 00 1 1100 0 ssss dddd iiii vvvvvvvv orr rd,rs,#iv OR, preserving CPSR, rs, to rd, with v ror i<<1 cccc 00 1 1100 1 ssss dddd iiii vvvvvvvv orrs rd,rs,#iv OR rs, to rd, with v ror i<<1 cccc 00 0 1101 0 0000 dddd iiiii 00 0 vvvv mov rd,rv,lsl #i Move, preserving CPSR, to rd, rv<>i cccc 00 0 1101 0 0000 dddd 00000 01 0 vvvv mov rd,rv,lsr #0x20 Move, preserving CPSR, to rd, rv>>32 cccc 00 0 1101 0 0000 dddd iiiii 10 0 vvvv mov rd,rv,asr #1 Move, preserving CPSR, to rd, rvą>>i cccc 00 0 1101 0 0000 dddd 00000 10 0 vvvv mov rd,rv,asr #0x20 Move, preserving CPSR, to rd, rvą>>32 cccc 00 0 1101 0 0000 dddd iiiii 11 0 vvvv mov rd,rv,ror #i Move, preserving CPSR, to rd, rv ror i cccc 00 0 1101 0 0000 dddd 00000 11 0 vvvv mov rd,rv,rrx #1 Move, preserving CPSR, to rd, rv rrx 1 cccc 00 0 1101 0 0000 dddd rrrr0 00 1 vvvv mov rd,rv,lsl rr Move, preserving CPSR, to rd, rv<>rr cccc 00 0 1101 0 0000 dddd rrrr0 11 1 vvvv mov rd,rv,ror rr Move, preserving CPSR, to rd, rv ror rr cccc 00 0 1101 1 0000 dddd iiiii 00 0 vvvv movs rd,rv,lsl #i Move to rd, rv<>i cccc 00 0 1101 1 0000 dddd 00000 01 0 vvvv movs rd,rv,lsr #0x20 Move to rd, rv>>32 cccc 00 0 1101 1 0000 dddd iiiii 10 0 vvvv movs rd,rv,asr #i Move to rd, rvą>>i cccc 00 0 1101 1 0000 dddd 00000 10 0 vvvv movs rd,rv,asr #0x20 Move to rd, rvą>>32 cccc 00 0 1101 1 0000 dddd iiiii 11 0 vvvv movs rd,rv,ror #i Move to rd, rv ror i cccc 00 0 1101 1 0000 dddd 00000 11 0 vvvv movs rd,rv,rrx #1 Move to rd, rv rrx 1 cccc 00 0 1101 1 0000 dddd rrrr0 00 1 vvvv movs rd,rv,lsl rr Move to rd, rv<>rr cccc 00 0 1101 1 0000 dddd rrrr0 11 1 vvvv movs rd,rv,ror rr Move to rd, rv ror rr cccc 00 1 1101 0 0000 dddd iiii vvvvvvvv mov rd,#iv Move, preserving CPSR, to rd, v ror i<<1 cccc 00 1 1101 1 0000 dddd iiii vvvvvvvv movs rd,#iv Move to rd, v ror i<<1 cccc 00 0 1110 0 ssss dddd iiiii 00 0 vvvv bic rd,rs,rv,lsl #i Bit clear, preserving CPSR, rs, to rd, by rv<>i cccc 00 0 1110 0 ssss dddd 00000 01 0 vvvv bic rd,rs,rv,lsr #0x20 Bit clear, preserving CPSR, rs, to rd, by rv>>32 cccc 00 0 1110 0 ssss dddd iiiii 10 0 vvvv bic rd,rs,rv,asr #i Bit clear, preserving CPSR, rs, to rd, by rvą>>i cccc 00 0 1110 0 ssss dddd 00000 10 0 vvvv bic rd,rs,rv,asr #0x20 Bit clear, preserving CPSR, rs, to rd, by rvą>>32 cccc 00 0 1110 0 ssss dddd iiiii 11 0 vvvv bic rd,rs,rv,ror #i Bit clear, preserving CPSR, rs, to rd, by rv ror i cccc 00 0 1110 0 ssss dddd 00000 11 0 vvvv bic rd,rs,rv,rrx #1 Bit clear, preserving CPSR, rs, to rd, by rv rrx 1 cccc 00 0 1110 0 ssss dddd rrrr0 00 1 vvvv bic rd,rs,rv,lsl rr Bit clear, preserving CPSR, rs, to rd, by rv<>rr cccc 00 0 1110 0 ssss dddd rrrr0 11 1 vvvv bic rd,rs,rv,ror rr Bit clear, preserving CPSR, rs, to rd, by rv ror rr cccc 00 0 1110 1 ssss dddd iiiii 00 0 vvvv bics rd,rs,rv,lsl #i Bit clear rs, to rd, by rv<>i cccc 00 0 1110 1 ssss dddd 00000 01 0 vvvv bics rd,rs,rv,lsr #0x20 Bit clear rs, to rd, by rv>>32 cccc 00 0 1110 1 ssss dddd iiiii 10 0 vvvv bics rd,rs,rv,asr #i Bit clear rs, to rd, by rvą>>i cccc 00 0 1110 1 ssss dddd 00000 10 0 vvvv bics rd,rs,rv,asr #0x20 Bit clear rs, to rd, by rvą>>32 cccc 00 0 1110 1 ssss dddd iiiii 11 0 vvvv bics rd,rs,rv,ror #i Bit clear rs, to rd, by rv ror i cccc 00 0 1110 1 ssss dddd 00000 11 0 vvvv bics rd,rs,rv,rrx #1 Bit clear rs, to rd, by rv rrx 1 cccc 00 0 1110 1 ssss dddd rrrr0 00 1 vvvv bics rd,rs,rv,lsl rr Bit clear rs, to rd, by rv<>rr cccc 00 0 1110 1 ssss dddd rrrr0 10 1 vvvv bics rd,rs,rv,asr rr Bit clear rs, to rd, by rvą>>rr cccc 00 0 1110 1 ssss dddd rrrr0 11 1 vvvv bics rd,rs,rv,ror rr Bit clear rs, to rd, by rv ror rr cccc 00 1 1110 0 ssss dddd iiii vvvvvvvv bic rd,rs,#iv Bit clear, preserving CPSR, rs, to rd, by v ror i<<1 cccc 00 1 1110 1 ssss dddd iiii vvvvvvvv bics rd,rs,#iv Bit clear rs, to rd, by v ror i<<1 cccc 00 0 1111 0 0000 dddd iiiii 00 0 vvvv mvn rd,rv,lsl #i Move NOT, preserving CPSR, to rd, rv<>i cccc 00 0 1111 0 0000 dddd 00000 01 0 vvvv mvn rd,rv,lsr #0x20 Move NOT, preserving CPSR, to rd, rv>>32 cccc 00 0 1111 0 0000 dddd iiiii 10 0 vvvv mvn rd,rv,asr #i Move NOT, preserving CPSR, to rd, rvą>>i cccc 00 0 1111 0 0000 dddd 00000 10 0 vvvv mvn rd,rv,asr #0x20 Move NOT, preserving CPSR, to rd, rvą>>32 cccc 00 0 1111 0 0000 dddd iiiii 11 0 vvvv mvn rd,rv,ror #i Move NOT, preserving CPSR, to rd, rv ror i cccc 00 0 1111 0 0000 dddd 00000 11 0 vvvv mvn rd,rv,rrx #1 Move NOT, preserving CPSR, to rd, rv rrx 1 cccc 00 0 1111 0 0000 dddd rrrr0 00 1 vvvv mvn rd,rv,lsl rr Move NOT, preserving CPSR, to rd, rv<>rr cccc 00 0 1111 0 0000 dddd rrrr0 11 1 vvvv mvn rd,rv,ror rr Move NOT, preserving CPSR, to rd, rv ror rr cccc 00 0 1111 1 0000 dddd iiiii 00 0 vvvv mvns rd,rv,lsl #i Move NOT to rd, rv<>i cccc 00 0 1111 1 0000 dddd 00000 01 0 vvvv mvns rd,rv,lsr #0x20 Move NOT to rd, rv>>32 cccc 00 0 1111 1 0000 dddd iiiii 10 0 vvvv mvns rd,rv,asr #i Move NOT to rd, rvą>>i cccc 00 0 1111 1 0000 dddd 00000 10 0 vvvv mvns rd,rv,asr #0x20 Move NOT to rd, rvą>>32 cccc 00 0 1111 1 0000 dddd iiiii 11 0 vvvv mvns rd,rv,ror #i Move NOT to rd, rv ror i cccc 00 0 1111 1 0000 dddd 00000 11 0 vvvv mvns rd,rv,rrx #1 Move NOT to rd, rv rrx 1 cccc 00 0 1111 1 0000 dddd rrrr0 00 1 vvvv mvns rd,rv,lsl rr Move NOT to rd, rv<>rr cccc 00 0 1111 1 0000 dddd rrrr0 11 1 vvvv mvns rd,rv,ror rr Move NOT to rd, rv ror rr cccc 00 1 1111 0 0000 dddd iiii vvvvvvvv mvn rd,#iv Move NOT, preserving CPSR, to rd, v ror i<<1 cccc 00 1 1111 1 0000 dddd iiii vvvvvvvv mvns rd,#iv Move NOT to rd, v ror i<<1 Processor status register instructions cccc 00 0 10 0 0 0 1111 dddd 000000000000 mrs rd,cpsr Move to rd, cpsr cccc 00 0 10 0 1 0 fsxc 1111 00000000 ssss msr cpsr_fsxc,rs Move to cpsr, rs masked to fsxc cccc 00 0 10 1 0 0 1111 dddd 000000000000 mrs rd,spsr Move to rd, spsr cccc 00 0 10 1 1 0 fsxc 1111 00000000 ssss msr spsr_fsxc,rs Move to spsr, rs masked to fsxc cccc 00 1 10 0 1 0 fsxc 1111 iiii vvvvvvvv msr cpsr_fsxc,#iv Move to cpsr, v ror i<<1 masked by fsxc cccc 00 1 10 1 1 0 fsxc 1111 iiii vvvvvvvv msr spsr_fsxc,#iv Move to spsr, v ror i<<1 masked by fsxc Multiply instructions cccc 000 0000 0 dddd 0000 vvvv 1001 ssss mul rd,rs,rv Multiply, preserving CPSR, to rd, rs by rv cccc 000 0000 1 dddd 0000 vvvv 1001 ssss muls rd,rs,rv Multiply, to rd, rs by rv cccc 000 0001 0 hhhh eeee vvvv 1001 ssss mla rd,rs,rv,re Multiply and accumulate, preserving CPSR, to rd, from re, rs by rv cccc 000 0001 1 hhhh eeee vvvv 1001 ssss mlas rd,rs,rv,re Multiply and accumulate, to rd, from re, rs by rv cccc 000 0100 0 hhhh llll vvvv 1001 ssss umull rh,rl,rs,rv Multiply, preserving CPSR, high to rd, low to rl, rs by rv cccc 000 0100 1 hhhh llll vvvv 1001 ssss umulls rh,rl,rs,rv Multiply, high to rd, low to rl, rs by rv cccc 000 0101 0 hhhh llll vvvv 1001 ssss umlal rh,rl,rs,rv Multiply and accumulate, preserving CPSR, high to rd, low to rl, rs by rv cccc 000 0101 1 hhhh llll vvvv 1001 ssss umlals rh,rl,rs,rv Multiply and accumulate, high to rd, low to rl, rs by rv cccc 000 0110 0 hhhh llll vvvv 1001 ssss smull rh,rl,rs,rv Signed multiply, preserving CPSR, high to rd, low to rl, rs by rv cccc 000 0110 1 hhhh llll vvvv 1001 ssss smulls rh,rl,rs,rv Signed multiply, high to rd, low to rl, rs by rv cccc 000 0111 0 hhhh llll vvvv 1001 ssss smlal rh,rl,rs,rv Signed multiply and accumulate, preserving CPSR, high to rd, low to rl, rs by rv cccc 000 0111 1 hhhh llll vvvv 1001 ssss smlals rh,rl,rs,rv Signed multiply and accumulate, high to rd, low to rl, rs by rv Load/store instructions cccc 01 0 0 0 0 0 0 dddd ssss vvvvvvvvvvvv str rs,[rd],#-v Store rs to rd and decrement d by v cccc 01 0 0 0 0 0 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs],#-v Load to rd, rs and decrement s by v cccc 01 0 0 0 0 1 0 dddd ssss vvvvvvvvvvvv strt rs,[rd],#-v Store, forced non-privileged access, rs to rd and decrement d by v cccc 01 0 0 0 0 1 1 ssss dddd vvvvvvvvvvvv ldrt rd,[rs],#-v Load, forced non-privileged access, to rd, rs and decrement s by v cccc 01 0 0 0 1 0 0 dddd ssss vvvvvvvvvvvv strb rs,[rd],#-v Store, 8-bit, rs to rd and decrement d by v cccc 01 0 0 0 1 0 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs],#-v Load, 8-bit, to rd, rs and decrement s by v cccc 01 0 0 0 1 1 0 dddd ssss vvvvvvvvvvvv strbt rs,[rd],#-v Store, 8-bit forced non-privileged access, rs to rd and decrement d by v cccc 01 0 0 0 1 1 1 ssss dddd vvvvvvvvvvvv ldrbt rd,[rs],#-v Load, 8-bit forced non-privileged access, to rd, rs and decrement s by v cccc 01 0 0 1 0 0 0 dddd ssss vvvvvvvvvvvv str rs,[rd],#v Store rs to rd and increment d by v cccc 01 0 0 1 0 0 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs],#v Load to rd, rs and increment s by v cccc 01 0 0 1 0 1 0 dddd ssss vvvvvvvvvvvv strt rs,[rd],#v Store, forced non-privileged access, rs to rd and increment d by v cccc 01 0 0 1 0 1 1 ssss dddd vvvvvvvvvvvv ldrt rd,[rs],#v Load, forced non-privileged access, to rd, rs and increment s by v cccc 01 0 0 1 1 0 0 dddd ssss vvvvvvvvvvvv strb rs,[rd],#v Store, 8-bit, rs to rd and increment d by v cccc 01 0 0 1 1 0 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs],#v Load, 8-bit, to rd, rs and increment s by v cccc 01 0 0 1 1 1 0 dddd ssss vvvvvvvvvvvv strbt rs,[rd],#v Store, 8-bit forced non-privileged access, rs to rd and increment d by v cccc 01 0 0 1 1 1 1 ssss dddd vvvvvvvvvvvv ldrbt rd,[rs],#v Load, 8-bit forced non-privileged access, to rd, rs and increment s by v cccc 01 0 1 0 0 0 0 dddd ssss vvvvvvvvvvvv str rs,[rd,#-v] Store rs to rd - v cccc 01 0 1 0 0 0 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs,#-v] Load to rd, rs - v cccc 01 0 1 0 0 1 0 dddd ssss vvvvvvvvvvvv str rs,[rd,#-v]! Store rs to rd - v and decrement d by v cccc 01 0 1 0 0 1 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs,#-v]! Load to rd, rs - v and decrement s by v cccc 01 0 1 0 1 0 0 dddd ssss vvvvvvvvvvvv strb rs,[rd,#-v] Store, 8-bit, rs to rd - v cccc 01 0 1 0 1 0 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs,#-v] Load, 8-bit, to rd, rs - v cccc 01 0 1 0 1 1 0 dddd ssss vvvvvvvvvvvv strb rs,[rd,#-v]! Store, 8-bit, rs to rd - v and decrement d by v cccc 01 0 1 0 1 1 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs,#-v]! Load, 8-bit, to rd, rs - v and decrement s by v cccc 01 0 1 1 0 0 0 dddd ssss vvvvvvvvvvvv str rs,[rd,#v] Store rs to rd + v cccc 01 0 1 1 0 0 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs,#v] Load to rd, rs + v cccc 01 0 1 1 0 1 0 dddd ssss vvvvvvvvvvvv str rs,[rd,#v]! Store rs to rd + v and increment d by v cccc 01 0 1 1 0 1 1 ssss dddd vvvvvvvvvvvv ldr rd,[rs,#v]! Load to rd, rs + v and increment s by v cccc 01 0 1 1 1 0 0 dddd ssss vvvvvvvvvvvv strb rs,[rd,#v] Store, 8-bit, rs to rd + v cccc 01 0 1 1 1 0 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs,#v] Load, 8-bit, to rd, rs + v cccc 01 0 1 1 1 1 0 dddd ssss vvvvvvvvvvvv strb rs,[rd,#v]! Store, 8-bit, rs to rd + v and increment d by v cccc 01 0 1 1 1 1 1 ssss dddd vvvvvvvvvvvv ldrb rd,[rs,#v]! Load, 8-bit, to rd, rs + v and increment s by v cccc 01 1 0 0 0 0 0 dddd ssss iiiii 00 0 vvvv str rs,[rd],-rv,lsl #i Store rs to rd and decrement d by rv<>i cccc 01 1 0 0 0 0 0 dddd ssss 00000 01 0 vvvv str rs,[rd],-rv.lsr #0x20 Store rs to rd and decrement d by rv>>32 cccc 01 1 0 0 0 0 0 dddd ssss iiiii 10 0 vvvv str rs,[rd],-rv,asr #i Store rs to rd and decrement d by rvą>>i cccc 01 1 0 0 0 0 0 dddd ssss 00000 10 0 vvvv str rs,[rd],-rv,asr #0x20 Store rs to rd and decrement d by rvą>>32 cccc 01 1 0 0 0 0 0 dddd ssss iiiii 11 0 vvvv str rs,[rd],-rv,ror #i Store rs to rd and decrement d by rv ror i cccc 01 1 0 0 0 0 0 dddd ssss 00000 11 0 vvvv str rs,[rd],-rv,rrx #1 Store rs to rd and decrement d by rv rrx 1 cccc 01 1 0 0 0 0 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs],-rv,lsl #i Load to rd, rs and decrement s by rv<>i cccc 01 1 0 0 0 0 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs],-rv,lsr #0x20 Load to rd, rs and decrement s by rv>>32 cccc 01 1 0 0 0 0 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs],-rv,asr #i Load to rd, rs and decrement s by rvą>>i cccc 01 1 0 0 0 0 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs],-rv,asr #0x20 Load to rd, rs and decrement s by rvą>>32 cccc 01 1 0 0 0 0 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs],-rv,ror #i Load to rd, rs and decrement s by rv ror i cccc 01 1 0 0 0 0 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs],-rv,rrx #1 Load to rd, rs and decrement s by rv rrx 1 cccc 01 1 0 0 0 1 0 dddd ssss iiiii 00 0 vvvv strt rs,[rd],-rv,lsl #i Store, forced non-privileged access, rs to rd and decrement d by rv<>i cccc 01 1 0 0 0 1 0 dddd ssss 00000 01 0 vvvv strt rs,[rd],-rv,lsr #0x20 Store, forced non-privileged access, rs to rd and decrement d by rv>>32 cccc 01 1 0 0 0 1 0 dddd ssss iiiii 10 0 vvvv strt rs,[rd],-rv,asr #i Store, forced non-privileged access, rs to rd and decrement d by rvą>>i cccc 01 1 0 0 0 1 0 dddd ssss 00000 10 0 vvvv strt rs,[rd],-rv,asr #0x20 Store, forced non-privileged access, rs to rd and decrement d by rvą>>32 cccc 01 1 0 0 0 1 0 dddd ssss iiiii 11 0 vvvv strt rs,[rd],-rv,ror #i Store, forced non-privileged access, rs to rd and decrement d by rv ror i cccc 01 1 0 0 0 1 0 dddd ssss 00000 11 0 vvvv strt rs,[rd],-rv,rrx #1 Store, forced non-privileged access, rs to rd and decrement d by rv rrx 1 cccc 01 1 0 0 0 1 1 ssss dddd iiiii 00 0 vvvv ldrt rd,[rs],-rv,lsl #i Load, forced non-privileged access, to rd, rs and decrement s by rv<>i cccc 01 1 0 0 0 1 1 ssss dddd 00000 01 0 vvvv ldrt rd,[rs],-rv,lsr #0x20 Load, forced non-privileged access, to rd, rs and decrement s by rv>>32 cccc 01 1 0 0 0 1 1 ssss dddd iiiii 10 0 vvvv ldrt rd,[rs],-rv,asr #i Load, forced non-privileged access, to rd, rs and decrement s by rvą>>i cccc 01 1 0 0 0 1 1 ssss dddd 00000 10 0 vvvv ldrt rd,[rs],-rv,asr #0x20 Load, forced non-privileged access, to rd, rs and decrement s by rvą>>32 cccc 01 1 0 0 0 1 1 ssss dddd iiiii 11 0 vvvv ldrt rd,[rs],-rv,ror #i Load, forced non-privileged access, to rd, rs and decrement s by rv ror i cccc 01 1 0 0 0 1 1 ssss dddd 00000 11 0 vvvv ldrt rd,[rs],-rv,rrx #1 Load, forced non-privileged access, to rd, rs and decrement s by rv rrx 1 cccc 01 1 0 0 1 0 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd],-rv,lsl #i Store, 8-bit, rs to rd and decrement d by rv<>i cccc 01 1 0 0 1 0 0 dddd ssss 00000 01 0 vvvv strb rs,[rd],-rv,lsr #0x20 Store, 8-bit, rs to rd and decrement d by rv>>32 cccc 01 1 0 0 1 0 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd],-rv,asr #i Store, 8-bit, rs to rd and decrement d by rvą>>i cccc 01 1 0 0 1 0 0 dddd ssss 00000 10 0 vvvv strb rs,[rd],-rv,asr #0x20 Store, 8-bit, rs to rd and decrement d by rvą>>32 cccc 01 1 0 0 1 0 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd],-rv,ror #i Store, 8-bit, rs to rd and decrement d by rv ror i cccc 01 1 0 0 1 0 0 dddd ssss 00000 11 0 vvvv strb rs,[rd],-rv,rrx #1 Store, 8-bit, rs to rd and decrement d by rv rrx 1 cccc 01 1 0 0 1 0 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs],-rv,lsl #i Load, 8-bit, to rd, rs and decrement s by rv<>i cccc 01 1 0 0 1 0 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs],-rv,lsr #0x20 Load, 8-bit, to rd, rs and decrement s by rv>>32 cccc 01 1 0 0 1 0 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs],-rv,asr #i Load, 8-bit, to rd, rs and decrement s by rvą>>i cccc 01 1 0 0 1 0 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs],-rv,asr #0x20 Load, 8-bit, to rd, rs and decrement s by rvą>>32 cccc 01 1 0 0 1 0 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs],-rv,ror #i Load, 8-bit, to rd, rs and decrement s by rv ror i cccc 01 1 0 0 1 0 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs],-rv,rrx #1 Load, 8-bit, to rd, rs and decrement s by rv rrx 1 cccc 01 1 0 0 1 1 0 dddd ssss iiiii 00 0 vvvv strbt rs,[rd],-rv,lsl #i Store, 8-bit forced non-privileged access, rs to rd and decrement d by rv<>i cccc 01 1 0 0 1 1 0 dddd ssss 00000 01 0 vvvv strbt rs,[rd],-rv,lsr #0x20 Store, 8-bit forced non-privileged access, rs to rd and decrement d by rv>>32 cccc 01 1 0 0 1 1 0 dddd ssss iiiii 10 0 vvvv strbt rs,[rd],-rv,asr #i Store, 8-bit forced non-privileged access, rs to rd and decrement d by rvą>>i cccc 01 1 0 0 1 1 0 dddd ssss 00000 10 0 vvvv strbt rs,[rd],-rv,asr #0x20 Store, 8-bit forced non-privileged access, rs to rd and decrement d by rvą>>32 cccc 01 1 0 0 1 1 0 dddd ssss iiiii 11 0 vvvv strbt rs,[rd],-rv,ror #i Store, 8-bit forced non-privileged access, rs to rd and decrement d by rv ror i cccc 01 1 0 0 1 1 0 dddd ssss 00000 11 0 vvvv strbt rs,[rd],-rv,rrx #1 Store, 8-bit forced non-privileged access, rs to rd and decrement d by rv rrx 1 cccc 01 1 0 0 1 1 1 ssss dddd iiiii 00 0 vvvv ldrbt rd,[rs],-rv,lsl #i Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rv<>i cccc 01 1 0 0 1 1 1 ssss dddd 00000 01 0 vvvv ldrbt rd,[rs],-rv,lsr #0x20 Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rv>>32 cccc 01 1 0 0 1 1 1 ssss dddd iiiii 10 0 vvvv ldrbt rd,[rs],-rv,asr #i Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rvą>>i cccc 01 1 0 0 1 1 1 ssss dddd 00000 10 0 vvvv ldrbt rd,[rs],-rv,asr #0x20 Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rvą>>32 cccc 01 1 0 0 1 1 1 ssss dddd iiiii 11 0 vvvv ldrbt rd,[rs],-rv,ror #i Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rv ror i cccc 01 1 0 0 1 1 1 ssss dddd 00000 11 0 vvvv ldrbt rd,[rs],-rv,rrx #1 Load, 8-bit forced non-privileged access, to rd, rs and decrement s by rv rrx 1 cccc 01 1 0 1 0 0 0 dddd ssss iiiii 00 0 vvvv str rs,[rd],rv,lsl #i Store rs to rd and increment d by rv<>i cccc 01 1 0 1 0 0 0 dddd ssss 00000 01 0 vvvv str rs,[rd],rv,lsr #0x20 Store rs to rd and increment d by rv>>32 cccc 01 1 0 1 0 0 0 dddd ssss iiiii 10 0 vvvv str rs,[rd],rv,asr #i Store rs to rd and increment d by rvą>>i cccc 01 1 0 1 0 0 0 dddd ssss 00000 10 0 vvvv str rs,[rd],rv,asr #0x20 Store rs to rd and increment d by rvą>>32 cccc 01 1 0 1 0 0 0 dddd ssss iiiii 11 0 vvvv str rs,[rd],rv,ror #i Store rs to rd and increment d by rv ror i cccc 01 1 0 1 0 0 0 dddd ssss 00000 11 0 vvvv str rs,[rd],rv,rrx #1 Store rs to rd and increment d by rv rrx 1 cccc 01 1 0 1 0 0 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs],rv,lsl #i Load to rd, rs and increment s by rv<>i cccc 01 1 0 1 0 0 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs],rv,lsr #0x20 Load to rd, rs and increment s by rv>>32 cccc 01 1 0 1 0 0 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs],rv,asr #i Load to rd, rs and increment s by rvą>>i cccc 01 1 0 1 0 0 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs],rv,asr #0x20 Load to rd, rs and increment s by rvą>>32 cccc 01 1 0 1 0 0 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs],rv,ror #i Load to rd, rs and increment s by rv ror i cccc 01 1 0 1 0 0 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs],rv,rrx #1 Load to rd, rs and increment s by rv rrx 1 cccc 01 1 0 1 0 1 0 dddd ssss iiiii 00 0 vvvv strt rs,[rd],rv,lsl #i Store, forced non-privileged access, rs to rd and increment d by rv<>i cccc 01 1 0 1 0 1 0 dddd ssss 00000 01 0 vvvv strt rs,[rd],rv,lsr #0x20 Store, forced non-privileged access, rs to rd and increment d by rv>>32 cccc 01 1 0 1 0 1 0 dddd ssss iiiii 10 0 vvvv strt rs,[rd],rv,asr #i Store, forced non-privileged access, rs to rd and increment d by rvą>>i cccc 01 1 0 1 0 1 0 dddd ssss 00000 10 0 vvvv strt rs,[rd],rv,asr #0x20 Store, forced non-privileged access, rs to rd and increment d by rvą>>32 cccc 01 1 0 1 0 1 0 dddd ssss iiiii 11 0 vvvv strt rs,[rd],rv,ror #i Store, forced non-privileged access, rs to rd and increment d by rv ror i cccc 01 1 0 1 0 1 0 dddd ssss 00000 11 0 vvvv strt rs,[rd],rv,rrx #1 Store, forced non-privileged access, rs to rd and increment d by rv rrx 1 cccc 01 1 0 1 0 1 1 ssss dddd iiiii 00 0 vvvv ldrt rd,[rs],rv,lsl #i Load, forced non-privileged access, to rd, rs and increment s by rv<>i cccc 01 1 0 1 0 1 1 ssss dddd 00000 01 0 vvvv ldrt rd,[rs],rv,lsr #0x20 Load, forced non-privileged access, to rd, rs and increment s by rv>>32 cccc 01 1 0 1 0 1 1 ssss dddd iiiii 10 0 vvvv ldrt rd,[rs],rv,asr #i Load, forced non-privileged access, to rd, rs and increment s by rvą>>i cccc 01 1 0 1 0 1 1 ssss dddd 00000 10 0 vvvv ldrt rd,[rs],rv,asr #0x20 Load, forced non-privileged access, to rd, rs and increment s by rvą>>32 cccc 01 1 0 1 0 1 1 ssss dddd iiiii 11 0 vvvv ldrt rd,[rs],rv,ror #i Load, forced non-privileged access, to rd, rs and increment s by rv ror i cccc 01 1 0 1 0 1 1 ssss dddd 00000 11 0 vvvv ldrt rd,[rs],rv,rrx #1 Load, forced non-privileged access, to rd, rs and increment s by rv rrx 1 cccc 01 1 0 1 1 0 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd],rv,lsl #i Store, 8-bit, rs to rd and increment d by rv<>i cccc 01 1 0 1 1 0 0 dddd ssss 00000 01 0 vvvv strb rs,[rd],rv,lsr #0x20 Store, 8-bit, rs to rd and increment d by rv>>32 cccc 01 1 0 1 1 0 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd],rv,asr #i Store, 8-bit, rs to rd and increment d by rvą>>i cccc 01 1 0 1 1 0 0 dddd ssss 00000 10 0 vvvv strb rs,[rd],rv,asr #0x20 Store, 8-bit, rs to rd and increment d by rvą>>32 cccc 01 1 0 1 1 0 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd],rv,ror #i Store, 8-bit, rs to rd and increment d by rv ror i cccc 01 1 0 1 1 0 0 dddd ssss 00000 11 0 vvvv strb rs,[rd],rv,rrx #1 Store, 8-bit, rs to rd and increment d by rv rrx 1 cccc 01 1 0 1 1 0 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs],rv,lsl #i Load, 8-bit, to rd, rs and decrement s by rv<>i cccc 01 1 0 1 1 0 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs],rv,lsr #0x20 Load, 8-bit, to rd, rs and decrement s by rv>>32 cccc 01 1 0 1 1 0 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs],rv,asr #i Load, 8-bit, to rd, rs and decrement s by rvą>>i cccc 01 1 0 1 1 0 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs],rv,asr #0x20 Load, 8-bit, to rd, rs and decrement s by rvą>>32 cccc 01 1 0 1 1 0 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs],rv,ror #i Load, 8-bit, to rd, rs and decrement s by rv ror i cccc 01 1 0 1 1 0 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs],rv,rrx #1 Load, 8-bit, to rd, rs and decrement s by rv rrx 1 cccc 01 1 0 1 1 1 0 dddd ssss iiiii 00 0 vvvv strbt rs,[rd],rv,lsl #i Store, 8-bit forced non-privileged access, rs to rd and increment d by rv<>i cccc 01 1 0 1 1 1 0 dddd ssss 00000 01 0 vvvv strbt rs,[rd],rv,lsr #0x20 Store, 8-bit forced non-privileged access, rs to rd and increment d by rv>>32 cccc 01 1 0 1 1 1 0 dddd ssss iiiii 10 0 vvvv strbt rs,[rd],rv,asr #i Store, 8-bit forced non-privileged access, rs to rd and increment d by rvą>>i cccc 01 1 0 1 1 1 0 dddd ssss 00000 10 0 vvvv strbt rs,[rd],rv,asr #0x20 Store, 8-bit forced non-privileged access, rs to rd and increment d by rvą>>32 cccc 01 1 0 1 1 1 0 dddd ssss iiiii 11 0 vvvv strbt rs,[rd],rv,ror #i Store, 8-bit forced non-privileged access, rs to rd and increment d by rv ror i cccc 01 1 0 1 1 1 0 dddd ssss 00000 11 0 vvvv strbt rs,[rd],rv,rrx #1 Store, 8-bit forced non-privileged access, rs to rd and increment d by rv rrx 1 cccc 01 1 0 1 1 1 1 ssss dddd iiiii 00 0 vvvv ldrbt rd,[rs],rv,lsl #i Load, 8-bit forced non-privileged access, to rd, rs and increment s by rv<>i cccc 01 1 0 1 1 1 1 ssss dddd 00000 01 0 vvvv ldrbt rd,[rs],rv,lsr #0x20 Load, 8-bit forced non-privileged access, to rd, rs and increment s by rv>>32 cccc 01 1 0 1 1 1 1 ssss dddd iiiii 10 0 vvvv ldrbt rd,[rs],rv,asr #i Load, 8-bit forced non-privileged access, to rd, rs and increment s by rvą>>i cccc 01 1 0 1 1 1 1 ssss dddd 00000 10 0 vvvv ldrbt rd,[rs],rv,asr #0x20 Load, 8-bit forced non-privileged access, to rd, rs and increment s by rvą>>32 cccc 01 1 0 1 1 1 1 ssss dddd iiiii 11 0 vvvv ldrbt rd,[rs],rv,ror #i Load, 8-bit forced non-privileged access, to rd, rs and increment s by rv ror i cccc 01 1 0 1 1 1 1 ssss dddd 00000 11 0 vvvv ldrbt rd,[rs],rv,rrx #1 Load, 8-bit forced non-privileged access, to rd, rs and increment s by rv rrx 1 cccc 01 1 1 0 0 0 0 dddd ssss iiiii 00 0 vvvv str rs,[rd,-rv,lsl #i] Store rs to rd - rv<>i cccc 01 1 1 0 0 0 0 dddd ssss 00000 01 0 vvvv str rs,[rd,-rv,lsr #0x20] Store rs to rd - rv>>32 cccc 01 1 1 0 0 0 0 dddd ssss iiiii 10 0 vvvv str rs,[rd,-rv,asr #i] Store rs to rd - rvą>>i cccc 01 1 1 0 0 0 0 dddd ssss 00000 10 0 vvvv str rs,[rd,-rv,asr #0x20] Store rs to rd - rvą>>32 cccc 01 1 1 0 0 0 0 dddd ssss iiiii 11 0 vvvv str rs,[rd,-rv,ror #i] Store rs to rd - rv ror i cccc 01 1 1 0 0 0 0 dddd ssss 00000 11 0 vvvv str rs,[rd,-rv,rrx #1] Store rs to rd - rv rrx 1 cccc 01 1 1 0 0 0 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs,-rv,lsl #i] Load to rd, rs - rv<>i cccc 01 1 1 0 0 0 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs,-rv,lsr #0x20] Load to rd, rs - rv>>32 cccc 01 1 1 0 0 0 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs,-rv,asr #i] Load to rd, rs - rvą>>i cccc 01 1 1 0 0 0 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs,-rv,asr #0x20] Load to rd, rs - rvą>>32 cccc 01 1 1 0 0 0 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs,-rv,ror #i] Load to rd, rs - rv ror i cccc 01 1 1 0 0 0 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs,-rv,rrx #1] Load to rd, rs - rv rrx 1 cccc 01 1 1 0 0 1 0 dddd ssss iiiii 00 0 vvvv str rs,[rd,-rv,lsl #i]! Store rs to rd - v and decrement d by rv<>i cccc 01 1 1 0 0 1 0 dddd ssss 00000 01 0 vvvv str rs,[rd,-rv,lsr #0x20]! Store rs to rd - v and decrement d by rv>>32 cccc 01 1 1 0 0 1 0 dddd ssss iiiii 10 0 vvvv str rs,[rd,-rv,asr #i]! Store rs to rd - v and decrement d by rvą>>i cccc 01 1 1 0 0 1 0 dddd ssss 00000 10 0 vvvv str rs,[rd,-rv,asr #0x20]! Store rs to rd - v and decrement d by rvą>>32 cccc 01 1 1 0 0 1 0 dddd ssss iiiii 11 0 vvvv str rs,[rd,-rv,ror #i]! Store rs to rd - v and decrement d by rv ror i cccc 01 1 1 0 0 1 0 dddd ssss 00000 11 0 vvvv str rs,[rd,-rv,rrx #1]! Store rs to rd - v and decrement d by rv rrx 1 cccc 01 1 1 0 0 1 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs,-rv,lsl #i]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd iiiii 01 0 vvvv ldr rd,[rs,-rv,lsr #i]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs,-rv,lsr #0x20]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs,-rv,asr #i]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs,-rv,asr #0x20]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs,-rv,ror #i]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 0 1 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs,-rv,rrx #1]! Load to rd, rs - v and decrement s by rv cccc 01 1 1 0 1 0 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd,-rv,lsl #i] Store, 8-bit, rs to rd - rv<>i cccc 01 1 1 0 1 0 0 dddd ssss 00000 01 0 vvvv strb rs,[rd,-rv,lsr #0x20] Store, 8-bit, rs to rd - rv>>32 cccc 01 1 1 0 1 0 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd,-rv,asr #i] Store, 8-bit, rs to rd - rvą>>i cccc 01 1 1 0 1 0 0 dddd ssss 00000 10 0 vvvv strb rs,[rd,-rv,asr #0x20] Store, 8-bit, rs to rd - rvą>>32 cccc 01 1 1 0 1 0 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd,-rv,ror #i] Store, 8-bit, rs to rd - rv ror i cccc 01 1 1 0 1 0 0 dddd ssss 00000 11 0 vvvv strb rs,[rd,-rv,rrx #1] Store, 8-bit, rs to rd - rv rrx 1 cccc 01 1 1 0 1 0 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs,-rv,lsl #i] Load, 8-bit, to rd, rs - rv<>i cccc 01 1 1 0 1 0 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs,-rv,lsr #0x20] Load, 8-bit, to rd, rs - rv>>32 cccc 01 1 1 0 1 0 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs,-rv,asr #i] Load, 8-bit, to rd, rs - rvą>>i cccc 01 1 1 0 1 0 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs,-rv,asr #0x20] Load, 8-bit, to rd, rs - rvą>>32 cccc 01 1 1 0 1 0 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs,-rv,ror #i] Load, 8-bit, to rd, rs - rv ror i cccc 01 1 1 0 1 0 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs,-rv,rrx #1] Load, 8-bit, to rd, rs - rv rrx 1 cccc 01 1 1 0 1 1 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd,-rv,lsl #i]! Store, 8-bit, rs to rd - rv<>i and decrement d by rv>>i cccc 01 1 1 0 1 1 0 dddd ssss 00000 01 0 vvvv strb rs,[rd,-rv,lsr #0x20]! Store, 8-bit, rs to rd - rv>>32 and decrement d by rv>>32 cccc 01 1 1 0 1 1 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd,-rv,asr #i]! Store, 8-bit, rs to rd - rvą>>i and decrement d by rvą>>i cccc 01 1 1 0 1 1 0 dddd ssss 00000 10 0 vvvv strb rs,[rd,-rv,asr #0x20]! Store, 8-bit, rs to rd - rvą>>32 and decrement d by rvą>>32 cccc 01 1 1 0 1 1 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd,-rv,ror #i]! Store, 8-bit, rs to rd - rv ror i and decrement d by rv ror i cccc 01 1 1 0 1 1 0 dddd ssss 00000 11 0 vvvv strb rs,[rd,-rv,rrx #1]! Store, 8-bit, rs to rd - rv rxx 1 and decrement d by rv rrx 1 cccc 01 1 1 0 1 1 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs,-rv,lsl #i]! Load, 8-bit, to rd, rs - rv<>i and decrement s by rv>>i cccc 01 1 1 0 1 1 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs,-rv,lsr #0x20]! Load, 8-bit, to rd, rs - rv>>32 and decrement s by rv>>32 cccc 01 1 1 0 1 1 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs,-rv,asr #i]! Load, 8-bit, to rd, rs - rvą>>i and decrement s by rvą>>i cccc 01 1 1 0 1 1 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs,-rv,asr #0x20]! Load, 8-bit, to rd, rs - rvą>>32 and decrement s by rvą>>32 cccc 01 1 1 0 1 1 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs,-rv,ror #i]! Load, 8-bit, to rd, rs - rv ror i and decrement s by rv ror i cccc 01 1 1 0 1 1 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs,-rv,rrx #1]! Load, 8-bit, to rd, rs - rv rxx 1 and decrement s by rv rxx 1 cccc 01 1 1 1 0 0 0 dddd ssss iiiii 00 0 vvvv str rs,[rd,rv,lsl #i] Store rs to rd + rv<>i cccc 01 1 1 1 0 0 0 dddd ssss 00000 01 0 vvvv str rs,[rd,rv,lsr #0x20] Store rs to rd + rv>>32 cccc 01 1 1 1 0 0 0 dddd ssss iiiii 10 0 vvvv str rs,[rd,rv,asr #i] Store rs to rd + rvą>>i cccc 01 1 1 1 0 0 0 dddd ssss 00000 10 0 vvvv str rs,[rd,rv,asr #0x20] Store rs to rd + rvą>>32 cccc 01 1 1 1 0 0 0 dddd ssss iiiii 11 0 vvvv str rs,[rd,rv,ror #i] Store rs to rd + rv ror i cccc 01 1 1 1 0 0 0 dddd ssss 00000 11 0 vvvv str rs,[rd,rv,rrx #1] Store rs to rd + rv rxx 1 cccc 01 1 1 1 0 0 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs,rv,lsl #i] Load to rd, rs + rv<>i cccc 01 1 1 1 0 0 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs,rv,lsr #0x20] Load to rd, rs + rv>>32 cccc 01 1 1 1 0 0 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs,rv,asr #i] Load to rd, rs + rvą>>i cccc 01 1 1 1 0 0 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs,rv,asr #0x20] Load to rd, rs + rvą>>32 cccc 01 1 1 1 0 0 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs,rv,ror #i] Load to rd, rs + rv ror i cccc 01 1 1 1 0 0 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs,rv,rrx #1] Load to rd, rs + rv rrx 1 cccc 01 1 1 1 0 1 0 dddd ssss iiiii 00 0 vvvv str rs,[rd,rv,lsl #i]! Store rs to rd + rv and increment d by rv<>i cccc 01 1 1 1 0 1 0 dddd ssss 00000 01 0 vvvv str rs,[rd,rv,lsr #0x20]! Store rs to rd + rv and increment d by rv>>32 cccc 01 1 1 1 0 1 0 dddd ssss iiiii 10 0 vvvv str rs,[rd,rv,asr #i]! Store rs to rd + rv and increment d by rvą>>i cccc 01 1 1 1 0 1 0 dddd ssss 00000 10 0 vvvv str rs,[rd,rv,asr #0x20]! Store rs to rd + rv and increment d by rvą>>32 cccc 01 1 1 1 0 1 0 dddd ssss iiiii 11 0 vvvv str rs,[rd,rv,ror #i]! Store rs to rd + rv and increment d by rv ror i cccc 01 1 1 1 0 1 0 dddd ssss 00000 11 0 vvvv str rs,[rd,rv,rrx #1]! Store rs to rd + rv and increment d by rv rrx 1 cccc 01 1 1 1 0 1 1 ssss dddd iiiii 00 0 vvvv ldr rd,[rs,rv,lsl #i]! Load to rd, rs + rv and increment s by rv<>i cccc 01 1 1 1 0 1 1 ssss dddd 00000 01 0 vvvv ldr rd,[rs,rv,lsr #0x20]! Load to rd, rs + rv and increment s by rv>>32 cccc 01 1 1 1 0 1 1 ssss dddd iiiii 10 0 vvvv ldr rd,[rs,rv,asr #i]! Load to rd, rs + rv and increment s by rvą>>i cccc 01 1 1 1 0 1 1 ssss dddd 00000 10 0 vvvv ldr rd,[rs,rv,asr #0x20]! Load to rd, rs + rv and increment s by rvą>>32 cccc 01 1 1 1 0 1 1 ssss dddd iiiii 11 0 vvvv ldr rd,[rs,rv,ror #i]! Load to rd, rs + rv and increment s by rv ror i cccc 01 1 1 1 0 1 1 ssss dddd 00000 11 0 vvvv ldr rd,[rs,rv,rrx #1]! Load to rd, rs + rv and increment s by rv rrx 1 cccc 01 1 1 1 1 0 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd,rv,lsl #i] Store, 8-bit, rs to rd + rv<>i cccc 01 1 1 1 1 0 0 dddd ssss 00000 01 0 vvvv strb rs,[rd,rv,lsr #0x20] Store, 8-bit, rs to rd + rv>>32 cccc 01 1 1 1 1 0 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd,rv,asr #i] Store, 8-bit, rs to rd + rvą>>i cccc 01 1 1 1 1 0 0 dddd ssss 00000 10 0 vvvv strb rs,[rd,rv,asr #0x20] Store, 8-bit, rs to rd + rvą>>32 cccc 01 1 1 1 1 0 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd,rv,ror #i] Store, 8-bit, rs to rd + rv ror i cccc 01 1 1 1 1 0 0 dddd ssss 00000 11 0 vvvv strb rs,[rd,rv,rrx #1] Store, 8-bit, rs to rd + rv rrx 1 cccc 01 1 1 1 1 0 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs,rv,lsl #i] Load, 8-bit, to rd, rs + rv<>i cccc 01 1 1 1 1 0 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs,rv,lsr #0x20] Load, 8-bit, to rd, rs + rv>>32 cccc 01 1 1 1 1 0 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs,rv,asr #i] Load, 8-bit, to rd, rs + rvą>>i cccc 01 1 1 1 1 0 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs,rv,asr #0x20] Load, 8-bit, to rd, rs + rvą>>32 cccc 01 1 1 1 1 0 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs,rv,ror #i] Load, 8-bit, to rd, rs + rv ror i cccc 01 1 1 1 1 0 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs,rv,rrx #1] Load, 8-bit, to rd, rs + rv rrx 1 cccc 01 1 1 1 1 1 0 dddd ssss iiiii 00 0 vvvv strb rs,[rd,rv,lsl #i]! Store, 8-bit, rs to rd + rv and increment d by rv<>i cccc 01 1 1 1 1 1 0 dddd ssss 00000 01 0 vvvv strb rs,[rd,rv,lsr #0x20]! Store, 8-bit, rs to rd + rv and increment d by rv>>32 cccc 01 1 1 1 1 1 0 dddd ssss iiiii 10 0 vvvv strb rs,[rd,rv,asr #i]! Store, 8-bit, rs to rd + rv and increment d by rvą>>i cccc 01 1 1 1 1 1 0 dddd ssss 00000 10 0 vvvv strb rs,[rd,rv,asr #0x20]! Store, 8-bit, rs to rd + rv and increment d by rvą>>32 cccc 01 1 1 1 1 1 0 dddd ssss iiiii 11 0 vvvv strb rs,[rd,rv,ror #i]! Store, 8-bit, rs to rd + rv and increment d by rv ror i cccc 01 1 1 1 1 1 0 dddd ssss 00000 11 0 vvvv strb rs,[rd,rv,rrx #1]! Store, 8-bit, rs to rd + rv and increment d by rv rrx 1 cccc 01 1 1 1 1 1 1 ssss dddd iiiii 00 0 vvvv ldrb rd,[rs,rv,lsl #i]! Load, 8-bit, to rd, rs + rv and increment s by rv<>i cccc 01 1 1 1 1 1 1 ssss dddd 00000 01 0 vvvv ldrb rd,[rs,rv,lsr #0x20]! Load, 8-bit, to rd, rs + rv and increment s by rv>>32 cccc 01 1 1 1 1 1 1 ssss dddd iiiii 10 0 vvvv ldrb rd,[rs,rv,asr #i]! Load, 8-bit, to rd, rs + rv and increment s by rvą>>i cccc 01 1 1 1 1 1 1 ssss dddd 00000 10 0 vvvv ldrb rd,[rs,rv,asr #0x20]! Load, 8-bit, to rd, rs + rv and increment s by rvą>>32 cccc 01 1 1 1 1 1 1 ssss dddd iiiii 11 0 vvvv ldrb rd,[rs,rv,ror #i]! Load, 8-bit, to rd, rs + rv and increment s by rv ror i cccc 01 1 1 1 1 1 1 ssss dddd 00000 11 0 vvvv ldrb rd,[rs,rv,rrx #1]! Load, 8-bit, to rd, rs + rv and increment s by rv rrx 1 Load/store instructions cccc 000 0 0 0 0 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd],-rr Store, 16-bit, rs to rd and decrement d by rr cccc 000 0 0 0 0 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs],-rr Load, 16-bit, to rd, rs and decrement s by rr cccc 000 0 0 0 0 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs],-rr Load signed, 8-bit, to rd, rs and decrement s by rr cccc 000 0 0 0 0 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs],-rr Load signed, 16-bit, to rd, rs and decrement s by rr cccc 000 0 0 1 0 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd],#-i Store, 16-bit, rs to rd and decrement d by i cccc 000 0 0 1 0 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs],#-i Load, 16-bit, to rd, rs and decrement s by i cccc 000 0 0 1 0 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs],#-i Load signed, 8-bit, to rd, rs and decrement s by i cccc 000 0 0 1 0 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs],#-i Load signed, 16-bit, to rd, rs and decrement s by i cccc 000 0 1 0 0 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd],rr Store, 16-bit, rs to rd and increment d by rr cccc 000 0 1 0 0 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs],rr Load, 16-bit, to rd, rs and increment s by rr cccc 000 0 1 0 0 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs],rr Load signed, 8-bit, to rd, rs and increment s by rr cccc 000 0 1 0 0 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs],rr Load signed, 16-bit, to rd, rs and increment s by rr cccc 000 0 1 1 0 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd],#i Store, 16-bit, rs to rd and increment d by i cccc 000 0 1 1 0 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs],#i Load, 16-bit, to rd, rs and increment s by i cccc 000 0 1 1 0 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs],#i Load signed, 8-bit, to rd, rs and increment s by i cccc 000 0 1 1 0 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs],#i Load signed, 16-bit, to rd, rs and increment s by i cccc 000 1 0 0 0 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd,-rr] Store, 16-bit, rs to rd - rr cccc 000 1 0 0 0 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs,-rr] Load, 16-bit, to rd, rs - rr cccc 000 1 0 0 0 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs,-rr] Load signed, 8-bit, to rd, rs - rr cccc 000 1 0 0 0 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs,-rr] Load signed, 16-bit, to rd, rs - rr cccc 000 1 0 0 1 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd,-rr]! Store, 16-bit, rs to rd - rr and decrement rd by rr cccc 000 1 0 0 1 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs,-rr]! Load, 16-bit, to rd, rs - rr and decrement rs by rr cccc 000 1 0 0 1 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs,-rr]! Load signed, 8-bit, to rd, rs - rr and decrement rs by rr cccc 000 1 0 0 1 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs,-rr]! Load signed, 16-bit, to rd, rs - rr and decrement rs by rr cccc 000 1 0 1 0 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd,#-i] Store, 16-bit, rs to rd - i and decrement rs by i cccc 000 1 0 1 0 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs,#-i] Load, 16-bit, to rd, rs - i and decrement rs by i cccc 000 1 0 1 0 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs,#-i] Load signed, 8-bit, to rd, rs - i and decrement rs by i cccc 000 1 0 1 0 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs,#-i] Load signed, 16-bit, to rd, rs - i and decrement rs by i cccc 000 1 0 1 1 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd,#-i]! Store, 16-bit, rs to rd - i and decrement rs by i cccc 000 1 0 1 1 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs,#-i]! Load, 16-bit, to rd, rs - i and decrement rs by i cccc 000 1 0 1 1 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs,#-i]! Load signed, 8-bit, to rd, rs - i and decrement rs by i cccc 000 1 0 1 1 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs,#-i]! Load signed, 16-bit, to rd, rs - i and decrement rs by i cccc 000 1 1 0 0 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd,rr] Store, 16-bit, rs to rd + rr cccc 000 1 1 0 0 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs,rr] Load, 16-bit, to rd, rs + rr cccc 000 1 1 0 0 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs,rr] Load signed, 8-bit, to rd, rs + rr cccc 000 1 1 0 0 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs,rr] Load signed, 16-bit, to rd, rs + rr cccc 000 1 1 0 1 0 dddd ssss 0000 1 01 1 rrrr strh rs,[rd,rr]! Store, 16-bit, rs to rd + rr and increment rd by rr cccc 000 1 1 0 1 1 ssss dddd 0000 1 01 1 rrrr ldrh rd,[rs,rr]! Load, 16-bit, to rd, rs + rr and increment rs by rr cccc 000 1 1 0 1 1 ssss dddd 0000 1 10 1 rrrr ldrsb rd,[rs,rr]! Load signed, 8-bit, to rd, rs + rr and increment rs by rr cccc 000 1 1 0 1 1 ssss dddd 0000 1 11 1 rrrr ldrsh rd,[rs,rr]! Load signed, 16-bit, to rd, rs + rr and increment rs by rr cccc 000 1 1 1 0 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd,#i] Store, 16-bit, rs to rd + i cccc 000 1 1 1 0 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs,#i] Load, 16-bit, to rd, rs + i cccc 000 1 1 1 0 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs,#i] Load signed, 8-bit, to rd, rs + i cccc 000 1 1 1 0 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs,#i] Load signed, 16-bit, to rd, rs + i cccc 000 1 1 1 1 0 dddd ssss iiii 1 01 1 iiii strh rs,[rd,#i]! Store, 16-bit, rs to rd + i and increment rd by i cccc 000 1 1 1 1 1 ssss dddd iiii 1 01 1 iiii ldrh rd,[rs,#i]! Load, 16-bit, to rd, rs + i and increment rs by i cccc 000 1 1 1 1 1 ssss dddd iiii 1 10 1 iiii ldrsb rd,[rs,#i]! Load signed, 8-bit, to rd, rs + i and increment rs by i cccc 000 1 1 1 1 1 ssss dddd iiii 1 11 1 iiii ldrsh rd,[rs,#i]! Load signed, 16-bit, to rd, rs + i and increment rs by i Psuedo-DMA instructions cccc 100 0 0 0 0 0 ssss dddddddddddddddd stmda rs,{rd} Store, post-decrementivly, rs to bit corrosponding registers cccc 100 0 0 0 0 1 dddd ssssssssssssssss ldmda rd,{rs} Load, post-decrementivly, to rd, bit corrosponding registers cccc 100 0 0 0 1 0 ssss dddddddddddddddd stmda rs!,{rd} Store, post-decrementivly, rs to bit corrosponding registers and decrement rs cccc 100 0 0 0 1 1 dddd ssssssssssssssss ldmda rd!,{rs} Load, post-decrementivly, to rd, bit corrosponding registers and decrement rd cccc 100 0 0 1 0 0 ssss dddddddddddddddd stmda rs,{rd}^ Store, post-decrementivly, forced non-privileged access, rs to bit corrosponding registers cccc 100 0 0 1 0 1 dddd ssssssssssssssss ldmda rd,{rs}^ Load, post-decrementivly, forced non-privileged access, to rd, bit corrosponding registers cccc 100 0 0 1 0 1 dddd 1sssssssssssssss ldmda rd,{rs}^ Load, post-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 0 0 1 1 0 ssss dddddddddddddddd stmda rs!,{rd}^ Store, post-decrementivly, forced non-privileged access, rs to bit corrosponding registers and decrement rs cccc 100 0 0 1 1 1 dddd ssssssssssssssss ldmda rd!,{rs}^ Load, post-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and decrement rd cccc 100 0 0 1 1 1 dddd 1sssssssssssssss ldmda rd!,{rs}^ Load, post-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 0 1 0 0 0 ssss dddddddddddddddd stmia rs,{rd} Store, post-incrementivly, rs to bit corrosponding registers cccc 100 0 1 0 0 1 dddd ssssssssssssssss ldmia rd,{rs} Load, post-incrementivly, to rd, bit corrosponding registers cccc 100 0 1 0 1 0 ssss dddddddddddddddd stmia rs!,{rd} Store, post-incrementivly, rs to bit corrosponding registers and increment rs cccc 100 0 1 0 1 1 dddd ssssssssssssssss ldmia rd!,{rs} Load, post-incrementivly, to rd, bit corrosponding registers and increment rd cccc 100 0 1 1 0 0 ssss dddddddddddddddd stmia rs,{rd}^ Store, post-incrementivly, forced non-privileged access, rs to bit corrosponding registers cccc 100 0 1 1 0 1 dddd ssssssssssssssss ldmia rd,{rs}^ Load, post-incrementivly, forced non-privileged access, to rd, bit corrosponding registers cccc 100 0 1 1 0 1 dddd 1sssssssssssssss ldmia rd,{rs}^ Load, post-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 0 1 1 1 0 ssss dddddddddddddddd stmia rs!,{rd}^ Store, post-incrementivly, forced non-privileged access, rs to bit corrosponding registers and increment rs cccc 100 0 1 1 1 1 dddd ssssssssssssssss ldmia rd!,{rs}^ Load, post-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and increment rd cccc 100 0 1 1 1 1 dddd 1sssssssssssssss ldmia rd!,{rs}^ Load, post-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 1 0 0 0 0 ssss dddddddddddddddd stmdb rs,{rd} Store, pre-decrementivly, rs to bit corrosponding registers cccc 100 1 0 0 0 1 dddd ssssssssssssssss ldmdb rd,{rs} Load, pre-decrementivly, to rd, bit corrosponding registers cccc 100 1 0 0 1 0 ssss dddddddddddddddd stmdb rs!,{rd} Store, pre-decrementivly, rs to bit corrosponding registers and decrement rs cccc 100 1 0 0 1 1 dddd ssssssssssssssss ldmdb rd!,{rs} Load, pre-decrementivly, to rd, bit corrosponding registers and decrement rd cccc 100 1 0 1 0 0 ssss dddddddddddddddd stmdb rs,{rd}^ Store, pre-decrementivly, forced non-privileged access, rs to bit corrosponding registers cccc 100 1 0 1 0 1 dddd ssssssssssssssss ldmdb rd,{rs}^ Load, pre-decrementivly, forced non-privileged access, to rd, bit corrosponding registers cccc 100 1 0 1 0 1 dddd 1sssssssssssssss ldmdb rd,{rs}^ Load, pre-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 1 0 1 1 0 ssss dddddddddddddddd stmdb rs!,{rd}^ Store, pre-decrementivly, forced non-privileged access, rs to bit corrosponding registers and decrement rs cccc 100 1 0 1 1 1 dddd ssssssssssssssss ldmdb rd!,{rs}^ Load, pre-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and decrement rd cccc 100 1 0 1 1 1 dddd 1sssssssssssssss ldmdb rd!,{rs}^ Load, pre-decrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 1 1 0 0 0 ssss dddddddddddddddd stmib rs,{rd} Store, pre-incrementivly, rs to bit corrosponding registers cccc 100 1 1 0 0 1 dddd ssssssssssssssss ldmib rd,{rs} Load, pre-incrementivly, to rd, bit corrosponding registers cccc 100 1 1 0 1 0 ssss dddddddddddddddd stmib rs!,{rd} Store, pre-incrementivly, rs to bit corrosponding registers and increment rs cccc 100 1 1 0 1 1 dddd ssssssssssssssss ldmib rd!,{rs} Load, pre-incrementivly, to rd, bit corrosponding registers and increment rd cccc 100 1 1 1 0 0 ssss dddddddddddddddd stmib rs,{rd}^ Store, pre-incrementivly, forced non-privileged access, rs to bit corrosponding registers cccc 100 1 1 1 0 1 dddd ssssssssssssssss ldmib rd,{rs}^ Load, pre-incrementivly, forced non-privileged access, to rd, bit corrosponding registers cccc 100 1 1 1 0 1 dddd 1sssssssssssssss ldmib rd,{rs}^ Load, pre-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR cccc 100 1 1 1 1 0 ssss dddddddddddddddd stmib rs!,{rd}^ Store, pre-incrementivly, forced non-privileged access, rs to bit corrosponding registers and increment rs cccc 100 1 1 1 1 1 dddd ssssssssssssssss ldmib rd!,{rs}^ Load, pre-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and increment rd cccc 100 1 1 1 1 1 dddd 1sssssssssssssss ldmib rd!,{rs}^ Load, pre-incrementivly, forced non-privileged access, to rd, bit corrosponding registers and SPSR to CPSR Load-store instructions cccc 00010 0 00 vvvv dddd 00001001 ssss swp rd,rs,[rv] Load, to rd, rv and store rs to rv cccc 00010 1 00 vvvv dddd 00001001 ssss swpb rd,rs,[rv] Load, 8-bit, to rd, rv and store, 8-bit, rs to rv Interrupt instruction cccc 1111 iiiiiiiiiiiiiiiiiiiiiiii swi #i Jump to 00000008; enter supervisor mode, IRQs disabled